A wideband high-linearity RF receiver front-end in CMOS

This paper presents a wideband high-linearity RF receiver-front-end, implemented in standard 0.18 /spl mu/m CMOS technology. The design employs a noise-canceling LNA in combination with two passive mixers, followed by lowpass-filtering and amplification at IF. The achieved bandwidth is >2 GHz, with a noise figure of 6.5 dB, +1 dBm IIP/sub 3/, +34.5 dBm IIP/sub 2/ and <50 kHz 1/f-noise corner frequency

An Analogue Front-End Test-Bed for Software Defined Radio

A Software Defined Radio (SDR) is a radio receiver and/or transmitter, whose characteristics can to a large extent be defined by software. Thus, an SDR can receive and/or transmit a wide variety of signals, supporting many different standards. In our research, we currently focus on a demonstrator that is able to receive both Bluetooth and HiperLAN/2. This helps us to identify problems associated with SDR, and will provide a test-bed for possible solutions to these problems. The two standards differ significantly in characteristics like frequency band, signal bandwidth and modulation type. Combining two different standards in one receiver appears to pose new design challenges. For example, in the wide frequency range that we want to receive, many strong signals\ud may exist. This leads to severe linearity requirements for wideband receivers. This paper describes some receiver architectures. One\ud design has been selected. This receiver has been built, and some measurement results are included

An Analogue Front-End Architecture for Software Defined Radio

A Software Defined Radio (SDR) is a radio receiver and/or transmitter, whose characteristics can to a large extent be defined by software. Thus, an SDR can receive and/or transmit a wide variety of signals, supporting many different standards. In our research, we currently focus on a demonstrator that is able to receive both Bluetooth and HiperLAN/2. This helps us to identify problems associated with SDR, and will provide a test-bed for possible solutions to these problems. The two standards differ significantly in characteristics like frequency band, signal bandwidth and modulation type. Combining two different standards in one receiver appears to pose new design challenges. For example, in the wide frequency range that we want to receive, many strong signals\ud may exist. This leads to severe linearity requirements for wideband receivers. This paper describes some receiver architectures. One\ud design has been selected. This receiver has been built, and some measurement results are included

Variable Bandwidth Analog Channel Filters for Software Defined Radio

An important aspect of Software Defined Radio is the ability to define the bandwidth of the filter that selects the desired channel. This paper first explains the importance of channel filtering. Then the advantage of analog channel filtering with a variable bandwidth in a Software Defined Radio is demonstrated. This is done by comparing the requirements of the analog-to-digital converter with and without an analog filter with a variable bandwidth. Then, a technique for channel filtering is described, in which two passive filters are combined to obtain a variable bandwidth. Passive filters have the advantage of high linearity, low noise and inherent energy efficiency. Some limitations of the concept are discussed. Finally, conclusions are drawn and our ideas for further research are presented

A Wideband Inductorless CMOS Front-End for Software Defined

The number of wireless communication links is witnessing tremendous growth and new standards are being introduced at high pace. These standards heavily rely on digital signal processing, making CMOS the first technology of choice. However, RF CMOS circuit development is costly and time consuming due to mask costs and design iterations. This pleads for a Software Defined Radio approach, in which one piece of flexible radio hardware is re-used for different applications and standards, downloadable and under software control. To the best of our knowledge, little work has been done in this field based on CMOS technology. Recently, a bipolar downconverter front-end has been proposed [1]. In CMOS, only wideband low-noise amplifiers have been proposed, and some CMOS tuner ICs for satellite reception (which have less stringent noise requirements because they are preceded by an outdoor low-noise converter). This paper presents a wideband RF downconverter frontend in 0.18 um CMOS (also published in [2]), designed in the context of a research project exploring the feasibility of software defined radio, using a combined Bluetooth/WLAN receiver as a vehicle. Usually, RF receivers are optimised for low power consumption. In contrast, we have taken the approach to optimise for flexibility. The paper discusses the main system and circuit design choices, and assesses the achievable performance via measurements on a front-end implemented in 0.18um CMOS. The flexible design achieves a 0.2-2.2 GHz -3 dB bandwidth, a gain of 25 dB with 6 dB noise figure and +1 dBm IIP3

Jitter requirements of the sampling clock in software radio receivers

The effective number of bits of an analog-to-digital converter (ADC) is not only limited by the quantization step inaccuracy but also by sampling time uncertainty. According to a commonly used model, the error caused by timing jitter, integrated over the whole bandwidth, should not be bigger than the quantization noise, for a full swing input signals at the maximum input frequency. This results in unfeasible phase noise requirements for the sampling clock in software radio receivers with direct RF sampling. However, for a radio receiver not the total integrated error is relevant, but only the error signal in the channel bandwidth. This paper explores the clock jitter requirements for a software radio application, using a more realistic model and taking into account the power spectrum of both the input signal and the spectrum of the sampling clock jitter. Using this model, we show that the clock jitter requirements are very similar to reciprocal mixing requirements of superheterodyne receivers

High-Q variable bandwidth passive filters for Software Defined Radio

An important aspect of Software Defined Radio is the ability to define the bandwidth of the filter that selects the desired channel. This paper describes a technique for channel filtering, in which two passive filters are combined to obtain a variable bandwidth. Passive filters have the advantage of high linearity, low noise and inherent energy efficiency. After an explanation of the concept, the requirements on the subsequent analog-todigital conversion are compared with those in a system where (part of) the channel selection is performed digitally. Some drawbacks of the concept are discussed. Finally, conclusions are drawn and our ideas for further research are presented

Cognitive radios for dynamic spectrum access - polyphase multipath radio circuits for dynamic spectrum access

Dynamic access of unused spectrum via a cognitive radio asks for flexible radio circuits that can work at an arbitrary radio frequency. This article reviews techniques to realize radios without resorting to frequency selective dedicated filters. In particular, a recently proposed polyphase multipath technique canceling harmonics and sidebands is discussed. Using this technique, a wideband and flexible power upconverter with a clean output spectrum has been realized on a CMOS chip, aiming at flexible radio transmitter application. Prototype chips can transmit at an arbitrary frequency between DC and 2.4 GHz. Unwanted harmonics and sidebands are more than 40 dB lower than the desired signal up to the 17th harmonic of the transmit frequenc

Jitter requirements of the sampling clock in software radio receivers

Abstract—The effective number of bits of an analog-to-digital converter (ADC) is not only limited by the quantization step inaccuracy but also by sampling time uncertainty. According to a commonly used model, the error caused by timing jitter, integrated over the whole bandwidth, should not be bigger than the quantization noise, for a full swing input signals at the maximum input frequency. This results in unfeasible phase noise requirements for the sampling clock in software radio receivers with direct RF sampling. However, for a radio receiver not the total integrated error is relevant, but only the error signal in the channel bandwidth. This paper explores the clock jitter requirements for a software radio application, using a more realistic model and taking into account the power spectrum of both the input signal and the spectrum of the sampling clock jitter. Using this model, we show that the clock jitter requirements are very similar to reciprocal mixing requirements of superheterodyne receivers. Index Terms—Analog-to-digital converter (ADC), jitter, mixer, sampling, software radio

A Combined Analogue+digital Software Defined Radio Receiver Front-end for Bluetooth and HiperLAN/2

The number of wireless communication links is witnessing tremendous growth and new standards are being introduced at high pace. However, circuit development is costly and time consuming due to mask costs and design iterations. Moreover, with ever-increasing radio standard complexity, these costs are increasing. This pleads for a Software Defined Radio approach, in which one piece of flexible radio hardware is re-used for different applications and standards, downloadable and under software control. A software defined radio receiver can -at different timesreceive signals of a multitude of standards, obliviating the need to design, manufacture, stock and carry around separate receivers for all contemporary radio standards. The presented design includes both the analogue and the digital front-end. A CMOS integrated analogue downconverter containing a low-noise amplifier, downconversion mixers and filters performs all analogue processing required between RF pre-filters and the analogue-to-digital converter. The real-time baseband processing is partly implemented on an ASIC (channel selection) and partly on a standard PC (demodulation). Using a standard PC further enhances the\ud flexibility of the design. The combined set-up is capable of receiving both Bluetooth and Hiperlan/2 signals. We conclude that an analog wide-band front-end with a flexible Sample-Rate Converter (SRC) combined with appropriate software on an inherently flexible PC forms a feasible architecture for Software Defined Radio